Utilize este identificador para referenciar este registo: http://hdl.handle.net/10071/29488
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dc.contributor.authorMiranda, I. D. S.-
dc.contributor.authorArora, A.-
dc.contributor.authorSusskind, Z.-
dc.contributor.authorSouza, J. S. A.-
dc.contributor.authorJadhao, M. P.-
dc.contributor.authorVillon, L. A. Q.-
dc.contributor.authorDutra, D. L. C.-
dc.contributor.authorLima, P. M. V.-
dc.contributor.authorFrança, F. M. G.-
dc.contributor.authorBreternitz Jr., M.-
dc.contributor.authorJohn, L. K.-
dc.contributor.editorCardoso, J. M. P., Jimborean, A., and Mentens, N.-
dc.date.accessioned2023-10-30T12:15:11Z-
dc.date.issued2023-
dc.identifier.citationMiranda, I. D. S., Arora, A., Susskind, Z., Souza, J. S. A., Jadhao, M. P., Villon, L. A. Q., Dutra, D. L. C., Lima, P. M. V., França, F. M. G., Breternitz Jr., M., & John, L. K. (2023). COIN: Combinational Intelligent Networks. In J. M. P. Cardoso, A. Jimborean, & N. Mentens (Eds.), 2023 IEEE 34th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE. https://doi.org/10.1109/ASAP57973.2023.00016-
dc.identifier.isbn979-8-3503-4685-5-
dc.identifier.issn2160-0511-
dc.identifier.urihttp://hdl.handle.net/10071/29488-
dc.description.abstractWe introduce Combinational Intelligent Networks (COIN), a machine learning technique that targets edge inference using low-resourced FPGAs or ASICs. COIN is an improvement on LogicWiSARD, a recent weightless neural network that achieves low power, small area, and high throughput. We convert the LogicWiSARD model into a binary neural network, train it using backpropagation, and then convert it to a COIN model. As a result, COIN can achieve higher accuracy than LogicWiSARD or it can require significantly fewer hardware resources when comparing models with similar accuracies. In comparison to a BNN implementation, FINN, small and large COIN models are more energy efficient demonstrating up to 11.5x higher inferences/Joule at similar accuracy. Our tool executes the complete flow, from training to RTL. and is publicly available.eng
dc.language.isoeng-
dc.publisherIEEE-
dc.relationinfo:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/UIDB%2F50008%2F2020/PT-
dc.relationUIDP/4466/2020-
dc.relationinfo:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/UIDB%2F04466%2F2020/PT-
dc.relation.ispartof2023 IEEE 34th International Conference on Application-specific Systems, Architectures and Processors (ASAP)-
dc.rightsembargoedAccess-
dc.subjectWeightless neural networkseng
dc.subjectLogicWiSARDeng
dc.subjectBinary neural networkseng
dc.subjectFPGAeng
dc.subjectASICeng
dc.titleCOIN: Combinational Intelligent Networkseng
dc.typeconferenceObject-
dc.event.title34th International Conference on Application-specific Systems, Architectures and Processors (ASAP)-
dc.event.typeConferênciapt
dc.event.locationPorto, Portugaleng
dc.event.date2023-
dc.peerreviewedyes-
dc.date.updated2023-10-30T12:12:16Z-
dc.description.versioninfo:eu-repo/semantics/acceptedVersion-
dc.identifier.doi10.1109/ASAP57973.2023.00016-
dc.subject.fosDomínio/Área Científica::Ciências Naturais::Ciências da Computação e da Informaçãopor
dc.subject.fosDomínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informáticapor
dc.date.embargo2025-10-01-
iscte.identifier.cienciahttps://ciencia.iscte-iul.pt/id/ci-pub-97244-
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